1. Field of the Invention
The present invention relates to a biasing circuit and a semiconductor memory device using the same. More particularly, the present invention relates to a biasing circuit for quickly outputting a stable bias output, and a semiconductor memory device using the same.
2. Description of the Related Art
Conventionally, in a semiconductor memory device, it is important that an access time required to read and write a data is made short so that the whole computer system can be speeded up.
In a conventional semiconductor memory device such as s nonvolatile memory and a ROM, a data of 1 bit is stored in a memory cell. A predetermined bias voltage is applied to the drain of a transistor in the memory cell when the stored data should be read out. At this time, the stored data is determined to be xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d based on whether or not a drain current is larger than a predetermined value. Generally, the drain voltage is increased as the drain current of the transistor becomes larger. Therefore, if the bias voltage applied to the drain of the memory cell transistor is not stable when the stored data should be read out, the drain current is also not stable. As a result, it is not possible to correctly determine whether the drain current is larger than the predetermined value.
In recent years, the data is sometimes stored in the memory cell in the form of multiple bits, e.g., in the form of 4 bits. In such a multi-bit memory device, the stored data is determined based on the small difference in the drain current. Therefore, the bias voltage applied to the drain of the memory cell transistor must be strictly set to a predetermined value. For this purpose, the performance of the sense amplifier is given as one of the important factors to determine the access time of the semiconductor memory device. For this reason, various studies have been accomplished so far. For example, the improvement of a sense amplifier for an EPROM is disclosed in Japanese Laid Open Patent Application (JP-A-Showa 63-142596) and Japanese Laid Open Patent Application (JP-A-Heisei 4-353699).
The structures of conventional semiconductor memory devices will be described with reference to FIGS. 1 and 2. FIGS. 1 and 2 are circuit diagrams showing examples of the structures of sense amplifier circuits 100 provided in the conventional semiconductor memory devices.
For example, the conventional semiconductor memory device is a nonvolatile memory which uses a floating gate type MOSFET as a memory cell, as shown in FIG. 1. The conventional semiconductor memory device is composed of a memory cell array 101 for data storage. Digit lines DL1 to DLn are increased in potential from the ground potential to a predetermined potential so that a data can be read out from the memory cell array 101 by the sense amplifier circuit 100. The sense amplifier circuit 100 is composed of a sense circuit 10, a reference circuit 110, and a data detecting circuit 201.
Also, the memory cell array 101 is composed of a plurality of word lines WL1 to WLm provided in a row direction and the plurality of digit line DL1 to DLn provided into a column direction. Each of memory cells 11311 to 1131n, . . . , 113m1 to 113mn is composed of a floating gate type MOSFET and is provided for one of intersections of the plurality of word lines WL1 to WLm and the plurality of digit line DL1 to DLn. That is, the memory cells of m rows and n columns are arranged in a matrix in the memory cell array 101. The floating gate type MOSFET as the memory cell 113ji (j=1 to m, i=1 to n) is connected with the j-th one of the word lines WL1 to WLm at the gate and with the i-th one of the digit lines DL1 to DLn at the drain, and is connected with the ground potential in the source.
Also, a reference cell array 102 is composed of one reference word line WLR provided in a row direction and one reference digit line DLR provided in a column direction. One reference cell 111 with the same structure as the memory cell 113ji is provided at an intersection of the reference word line WLR and the reference digit line DLR. The reference cell 111 is connected with the reference word line WLR at the gate, and with reference digit line DLR at the drain and is connected with the ground potential at the source. In this example, the reference word line WLR and the reference DLR are provided to the reference cell array 102, and only one MOSFET is provided as the reference cell 111.
A row decoder 104 is connected with the word lines WL1 to WL1 in the memory cell array 101 and the column decoder 105 is connected to a column selector 103. The row decoder 104 and the column decoder 103 are supplied with an address signal (not shown). The row decoder 104 activates one of the word lines WL1 to WLm directly in accordance with the address signal. Also, the column decoder 103 connects one of the digit lines DL1 to DLn with the sense amplifer circuit 100 through the column selector 103 in accordance with the address signal.
The column selector 103 is composed of MOSFETs 1071 to 107n for carrying out digit line selection in response to the output of the column decoder 105 such that one of digit lines DL1 to DLn is selectively connected with the sense circuit 10. The sources of the MOSFETs 1071 to 107n in the column selector 103 are connected with the respective digit lines DL1 to DLn, and the drains thereof is commonly connected to the sence circuit 10 provided in the sense amplifier circuit 100.
Further, in the semiconductor memory device, one biasing circuit 20 is provided in the sence circuit 10 for the plurality of digit lines DL1 to DLn. Also, one MOSFET 106 with the same size as MOSFETs 1071 to 107n of the column selector 103 is connected with the reference digit line DLR. The gate of the MOSFET 106 is connected with the power supply voltage. The drain of the MOSFET 106 which is provided for the reference cell array 102, is connected with the reference circuit 110.
In FIGS. 1 and 2, the word line WLj is selected by the row decoder 104 and the digit line DLi is selected by the column decoder 105 through the column selector 103. The case to sense a stored data of the memory cell 113ji which is connected with the word line WLj and the digit line DLi will be described as an example.
As shown in FIG. 1, the output terminals of the sense circuit 10 and reference circuit 110 are connected with a data detecting circuit 201 through signal lines LDi and LREF, respectively. The data detecting circuit 201 compares a detection voltage VDi on the signal line LDi and a reference voltage VREF on the signal line LREF, and determines the stored data of the selected memory cell. An output buffer (not shown) is connected on the output side of the data detecting circuit 201 and outputs the stored data from the data detecting circuit 201.
The memory cells 113ji (11311 to 113in, . . . , 113m1 to 113mn) and 111 of the nonvolatile memory store data based on whether or not electrons are injected to the floating gate. When the stored data of memory cell 113ji should be read, a predetermined voltage is applied to the memory cell 113ji by the biasing circuit 20 in the sense circuit 10. As a result, the stored data is determined based on whether or not a current flows through the selected memory cell 113ji. That is, in the memory cell in which electrons have been injected to the floating gate, the drain current does not flow even if a signal with a high level is supplied to the gate when the memory cell 113ji is set to a selected state. Oppositely, in the memory cell in which the electrons are pulled out of the floating gate, the drain current flows when the signal with the high level is supplied to the gate of the memory cell transistor in the cell 113ji in the selected state. On the other hand, a predetermined reference current always flows through the reference cell 111 which is provided in the reference cell array 102, because electrons are not injected or a predetermined quantity of electrons are injected.
As described above, in the conventional example of the nonvolatile memory, it corresponds to the stored data of xe2x80x9c1xe2x80x9d that electrons are injected to the floating gate, and it corresponds to the stored data of xe2x80x9c0xe2x80x9d that electrons are pulled out from the floating gate. However, sometimes there is a case opposite to the above.
An N-channel transistor 212 of the reference circuit 110 and an N-channel transistor 202 in the sense circuit 10 operate as load resistances. The N-channel transistors 212 and 202 convert the currents flowing through the reference digit line DLR and the digit line DLi into the voltages to be supplied to the data detecting circuit 201, respectively. Generally, the current supply capability of the transistor 212 is set larger than the current supply capability of the transistor 202. Even if the current with the same magnitude flows through each of the reference the digit line DLR and the digit line DLi, the voltage drop in the transistor 202 is larger than that in the transistor 212.
Now, it is supposed that the voltage generated in the drain of the transistor 212 by the reference current which flows through the reference cell 111 is a reference voltage VREF. Also, it is supposed that the detection voltages VDi generated in the transistor 202 by the current which flows through the memory cell 113ji in the on or off state are VDion or VDioff. At this time, the reference voltage VREF is generally set to be a middle voltage between the reference voltages VDioff and VDion. Therefore, if the detection voltage VDi is higher than the reference voltage VREF, the data detecting circuit 201 determines the memory cell 113ji to be in the off state of the data of xe2x80x9c0xe2x80x9d. Also, oppositely, if the detection voltage VDi is lower than the reference voltage VREF, the data detecting circuit 201 determines the memory cell 113ji to be in the on state of the data of xe2x80x9c1xe2x80x9d. Based on this determining result, the data detecting circuit 201 outputs a read data DOUTi.
As shown in FIG. 1, the biasing circuit 20 supplies a bias voltage to the digit line DLi when a sense amplifier operation enable signal SAE 30 is in a low level. Also, the biasing circuit 20 stops the supply of the bias voltage when the sense amplifier operation enable signal SAE 30 is in the high level. The biasing circuit 120 on the side of the reference digit line DLR operates in the same way.
The sense amplifier operation enable signal SAE 30 is used for the purpose that the bias voltage is supplied to the digit line DLi only in the reading operation. As a result, the period during which the current flows through the memory cell 113ji is made short, resulting in reduction of the power consumption of the semiconductor memory device. Thus, the sense amplifier operation enable signal SAE 30 is not a signal indispensable for the reading operation.
When the row decoder 104 activates the word line WLj, the memory cell 113ji is left in the off state in which electrons are injected, i.e., the stored data is xe2x80x9c1xe2x80x9d. Therefore, no current flows through the digit line DLi. As a result, the detection voltage VDi is set to the voltage VDioff which is higher than the reference voltage VREF. Oppositely, when electrons are pulled out from the selected memory cell 113ji, i.e., when the stored data is xe2x80x9c0xe2x80x9d, the memory cell 113ji is set to the on state and the detection voltage VDi is set to the voltage VDion which is lower than the reference voltage VREF. The voltage difference between the reference voltage VREF and the detection voltage VDion is detected by the data detecting circuit 201 as mentioned above. That is, the data detecting circuit 201 determines that the memory cell is in the state that electrons are injected to the floating gate of the memory cell 113ji, i.e., the stored data of the memory cell 113ji is xe2x80x9c1xe2x80x9d, when VDi (=VDioff) greater than VREF. On the other hand, the data detecting circuit 201 determines that electrons are pulled out from the floating gate of the memory cell 113ji, i.e., that the stored data of the memory cell 113ji is xe2x80x9c0xe2x80x9d, when VDi (=VDion) less than VREF.
Next, the sense amplifier circuit 100 provided in the semiconductor memory device shown in FIG. 1 will be described. The sense amplifier circuit 100 is composed of the sense circuit 10, the reference circuit 110 and the data detecting circuit 201. The sense circuit 10 is activated in response to the sense amplifier operation enable signal SAE 30 to supply a first predetermined voltage to the digit line DLi. The sense circuit 10 generates the detection voltage VDi based on the read data from the selected memory cell 113ji. The sense circuit 10 is composed of the biasing circuit 20 which supplies a second predetermined voltage to the digit line DLR and a load section 70 connected with the biasing circuit 20. The biasing circuit 20 is composed of a feed-back circuit 40 and an N-channel transistor 203. The feed-back circuit 40 is composed of a P-channel transistor 204 and N-channel transistors 205 and 302. The source of the P-channel transistor 204 is connected with the power supply voltage and the drain thereof is connected with the drains of the N-channel transistors 205 and 302. The sources of the N-channel transistors 205 and 302 are grounded.
Also, the sense amplifier operation enable signal SAE 30 is supplied to the gates of the P-channel transistor 204 and N-channel transistor 302. The sense amplifier operation enable signal SAE 30 is set to the high level in the state other than the reading operation, so that the transistor 204 is set to the off state and the transistor 302 is set to the on state. Therefore, the signal line FBi is set to the low level and the digit line DLi is also set to the low level. The sense amplifier operation enable signal SAE 30 is set to the low level during the reading operation. Therefore, the transistor 204 is turned on and the transistor 302 is turned off. As a result, the signal line FBi is set to a third predetermined voltage and the digit line DLi is also biased to the first predetermined voltage.
Since the transistor 203 operates as a source follower when the signal line FBi is set to the first predetermined voltage, the transistor 203 outputs the voltage VD0 as much as the level of signal line FBi. The voltage VD0 is supplied to the gate of the N-channel transistor 205 so that the transistor 205 passes a predetermined quantity of current. Because the transistor 205 passes a quantity of current more than the predetermined current when the voltage on the digit line DLi is higher than the third predetermined voltage, the transistor 205 decreases the voltage on the signal line FBi. When the voltage on the signal line FBi is decreased, the transistor 203 decreases the voltage on the digit line DLi. Oppositely, because the transistor 205 passes a quantity of current which are fewer than the predetermined quantity of current when the voltage on the digit line DLi is lower than the third predetermined voltage, the transistor 205 increases the voltage on the signal line FBi. When the voltage on the signal line FBi is increased, the transistor 203 increases the voltage on the digit line DLi. In this way, the biasing circuit 20 make the digit line DLi settle to the third predetermined bias voltage, even if the voltage on the digit line DLi changes.
Also, the load section 70 is composed of the N-channel transistor 202. Because the drain of the N-channel transistor 202 and the gate thereof are connected with the power supply voltage, the N-channel transistor 202 operates as a constant current circuit. An output from the feed-back circuit 40 is supplied to the gate of the N-channel transistor 203 so that the drain of the memory cell 113ji is biased to the third predetermined voltage. As a result, the predetermined quantity of drain current flows through the memory cell 113ji so that the detection voltage VDi is generated in the load section 70.
On the other hand, the reference circuit 110 supplies the reference digit line DLR with a fourth predetermined voltage and generates the reference voltage VREF based on the data of the reference cell 111. The reference circuit 110 is composed of the reference biasing circuit 120 which supplies the reference digit line DLR with a fourth predetermined voltage and the load section 170 which is connected with the reference biasing circuit 120. The reference biasing circuit 120 and the load section 170 have the same structures as those of the biasing circuit 20 and load section 70 in the sense circuit 10, respectively. That is, the reference biasing circuit 120 is composed of a feed-back circuit 140 and an N-channel transistor 213.
The feed-back circuit 140 is composed of a P-channel transistor 214 and N-channel transistors 215 and 312. Also, the load section 170 is composed of an N-channel transistor 212. A transistor having a resistance smaller than the N-channel transistor 202 in the sense circuit 10 is used as the N-channel transistor 212. Thus, the load section 170 is set to the middle voltage between the detection voltage of the memory cell 113 in the on state and the detection voltage of the memory cell 113ji in the off state. The reference biasing circuit 120 biases the reference bit line LDR to a predetermined voltage when the sense amplifier operation enable signal SAE 130 is supplied to the gates of the P-channel transistor 214 and N-channel transistor 312 in the feed-back circuit 140 so that the feed-back circuit 140 operates.
Next, the biasing circuit 20 in the sense circuit 10 which is provided in the sense amplifier circuit 100 of the semiconductor memory device shown in FIG. 1 will be described in detail.
As mentioned above, in the biasing circuit 20, when the sense amplifier operation enable signal SAE 30 is set to the low level in case of the reading operation, the P-channel transistor 204 is set to the on state, so that the voltage on the signal line FBi is increased. Also, the source of the N-channel transistor 203, i.e., the voltage of the digit line DLi is set to voltage corresponding to the voltage on the signal line FBi. In response to the set voltage, the current is fed back to the gate of the N-channel transistor 205 so that a predetermined quantity of current flows through the N-channel transistor 205. Therefore, the voltage on the signal line FBi converges to the first predetermined voltage. Because the voltage on the signal line FBi is biased to the first predetermined voltage, the voltage on the digit line DLi is biased to the third predetermined voltage. Also, the biased voltage is applied to the memory cell 113ji. This is a precharging process.
The detection voltage VDi corresponding to the current which flows through the memory cell 113ji is outputted from the data detecting circuit 201. At this time, in the reference biasing circuit 120, the sensing of the voltage difference between the detection voltage VDi and the reference voltage VREF is carried out in the data detecting circuit 201 because the increasing operation of the voltage on the reference digit line DLR is carried out and the reference voltage VREF is outputted from the data detecting circuit 201. This operation is a sensing process.
In a case where the content of the memory cell 113ji is xe2x80x9c1xe2x80x9d, when the sense amplifier operation enable signal SAE 30 is set to the low level, the voltage of the load section 70 is set to the voltage VDioff which is higher than the reference voltage VREF through the abovementioned operation. On the other hand, in a case where the stored data of xe2x80x9c0xe2x80x9d is read, because electrons are pulled out from the floating gate of the memory cell which is connected with the digit line DLi, the current flows through the memory cell. Therefore, the voltage drops are caused in the load section 70. The voltage of the load section 70 is set to the detection voltage VDion which is lower than the reference voltage VREF.
On the other hand, because the memory cell 106 connected with the digit line DLR is set to the state of xe2x80x9c0xe2x80x9d in the reference circuit 110, current flows through the N-channel transistor 212 so that the voltage drop is caused. Here, because the N-channel transistor 212 has the resistance smaller than the N-channel transistor 202, the reference voltage VREF is set to the middle voltage between the detection voltages VDioff and VDion.
As a result, when the stored data of xe2x80x9c1xe2x80x9d of the memory cell 113ji in the memory cell array 101 should be read, the data detecting circuit 201 outputs xe2x80x9c0xe2x80x9d as the output DOUTi, because the detection voltage VDi is higher than the reference voltage VREF (VDi=VDioff). On the other hand, when the stored data xe2x80x9c0xe2x80x9d of the memory cell 113ji in the memory cell array 101 should be read, the data detecting circuit 201 outputs the data of xe2x80x9c1xe2x80x9d, because the read voltage VDi is lower than the reference voltage VREF (VDi=VDion).
Also, the second conventional example of the semiconductor memory device is shown in FIG. 2. The second conventional example of the semiconductor memory device shown in FIG. 2 has approximately the same structure as that of the sense amplifier circuit 100 in the first conventional example of the semiconductor memory device shown in FIG. 1. However, inverters 208 and 218 are provided in the input terminals of the sense circuit 10 and reference circuit 110 for the sense amplifier operation enable signal SAE 30, respectively. Also, in the biasing circuit 20 and 120, N-channel transistors 206 and 216 are provided to the output terminals of the inverters 208 and 218 instead of the P-channel transistors 204 and 214, unlike the sense amplifier circuit 100 of FIG. 1. These points are different between the first and second conventional examples.
However, in the conventional semiconductor memory devices shown in FIG. 1 and FIG. 2, there are the following problems. That is, as described above, the performance improvement of the sense amplifier circuit is needed to respond to the high speed access of the semiconductor memory device. As a method to attempt the performance improvement of the sense amplifier circuit, there is the high efficiency and stabilization of the biasing circuit provided in the sense amplifier circuit. In the biasing circuit 20 of the sense circuit 10 provided in the sense amplifier circuit 100 of the conventional semiconductor memory device shown in FIG. 1, the P-channel transistor 204 is provided on the side of power supply voltage Vcc. When the P-channel transistor is used in the operation range of the above-mentioned biasing circuit, the voltage drop between the drain and the source is generally large to a small change of drain current. For this reason, when the P-channel transistor 204 is used on the side of power supply voltage Vcc in the biasing circuit 20 of the sense circuit 10, the load differential resistance becomes large so that the amplitude of the voltage on the signal line FBi becomes large.
Also, the source voltage (FBi) of the transistor 204 is set to approximately 0 V immediately after the reading operation is started, and the high level voltage of Vcc is supplied to the gate as the signal SAE. Also, the voltage difference between the gate and the source in the transistor 204 is about Vcc. Therefore, the transistor 204 operates at maximum drain current drive ability. Thus, the precharging process can be carried out at high speed to increase the degit line DLi to the third predetermined voltage.
However, in the conventional biasing circuit 20 shown in FIG. 1, because the P-channel transistor 204 is provided on the side of the power supply voltage, the biasing circuit 20 responds sensitively to change of the voltage on the digit line LDi due to noise. For this reason, it is difficult to stably carry out the sensing operation in which the data detecting circuit 201 compares the detection voltage VDi and the reference voltage VDREF. Also, there is a risk that the data detecting circuit 201 erroneously determines the stored data depending on the noise quantity. Moreover, because it takes a long time until the detection voltage VDi is stabilized in the sense circuit 10 when the degit line DLi is increased at high speed to the third predetermined voltage, the access time became rather long.
On the other hand, in the sense amplifier circuit 100 provided in the conventional semiconductor memory device shown in FIG. 2, the N-channel transistor 206 is provided on the side of power supply voltage Vcc in the biasing circuit 20 of the sense circuit 10. In the N-channel transistor 206, the variation of the voltage drop between the drain and the source is small to the small change of the drain current. Therefore, even if the voltage on the digit line LDi changes due to noise so that the influence of the voltage change is fed back via the N-channel transistor 205, the change of the voltage on the signal line FBi is small, compared with the sense circuit 10 in the semiconductor memory device shown in FIG. 1. Therefore, the sensing operation of the sense circuit 10 shown in FIG. 2 is not prevented.
However, if the N-channel transistor 206 is arranged on the side of the power supply voltage, the output of the feed-back circuit 40 shown in FIG. 2 is set to a voltage lower than the power supply voltage Vcc by the threshold voltage (VTN) of the transistor 206. Therefore, the voltage between the gate and the source in the transistor 206 becomes small so that the current drive ability of the transistor 206 is decreased. Therefore, the gate of the transistor 203 can not be rapidly increased in voltage. Moreover, the amplitude of the voltage on the signal FBi of the feed-back circuit 40 is limited to the level of about (Vcc to VTN) as the upper limit. Also, the transistor 203 can not carry out the precharging operation to the digit line LDi at high speed. As a result, it takes a long time to increase the voltage to a voltage level sufficient for the data detecting circuit 201 to carry out the sensing operation of the detection voltage VDi and the reference voltage VREF. As a result, the reading operation of the data from the memory cell 113ji becomes late.
In addition, in recent years, the power supply voltage Vcc of the semiconductor memory device is made low for consumption power saving in the whole semiconductor memory device. Therefore, the influence of the voltage drop due to the threshold voltage VTN became larger, compared with the conventional semiconductor memory device. For example, the influence of the voltage drop due to the above-mentioned threshold voltage VTN is larger, when the power supply voltage is set to 3 V, compared with the influence of the voltage drop due to the threshold voltage VTN, when the conventional power supply voltage Vcc is set to 5 V.
The above problems cause further increase of the time required for the detection voltage VDi to reach an enough voltage for the sensing operation and the time required to determine the stored data of the memory cell 113ji by the data detecting circuit 201.
Also, as a memory capacity is increased, the semiconductor memory device has been a larger size, so that the wiring line length in the chip of the semiconductor memory device becomes long Thus, the parasitic capacity and wiring resistance of the wiring line are increased. In the conventional biasing circuit, there is the contradiction that the stability of the stationary state is broken, when the wiring line with a large parasitic capacity is tried to rapidly increase, and the voltage increasing characteristic is degraded when the stability of the wiring line is tried to be improved.
Therefore, an object of the present invention is to provide a semiconductor memory device with a biasing circuit which can increase a bias output rapidly to a predetermined voltage.
Another object of the present invention is to provide a semiconductor memory device with a biasing circuit, in which the bias output can be rapidly stabilized.
Still another object of the present invention is to provide a semiconductor memory device with a biasing circuit, in which the reading operation of a stored data can be speeded up.
In order to achieve an aspect of the present invention, a biasing circuit includes an increasing circuit, a supplying circuit, a bias outputting circuit and a bias outputting circuit. The increasing circuit outputs a drive voltage, and the supplying circuit is connected in parallel to the increasing circuit and outputs a drive voltage. The bias outputting circuit outputs a bias output to a biased circuit in response to the drive voltage from the increasing circuit or the drive voltage from the supplying circuit. The control circuit controls the increasing circuit and the supplying circuit based on the bias output from the bias outputting circuit.
The increasing circuit includes a P-channel transistor having a source which is operatively connected to a power supply potential, a gate which is operatively connected to a ground potential, and a drain which is operatively connected to the bias outputting circuit. The supplying circuit includes an N-channel transistor having a drain which is operatively connected to the power supply potential, a gate which is operatively connected to the power supply potential, and a source which is operatively connected to the bias outputting circuit. The P-channel transistor and the N-channel transistor are connected in parallel.
The control circuit may include an N-channel control transistor having a drain which is connected to the increasing circuit and the supplying circuit, a gate which is operatively connected to the bias output from the bias outputting circuit, and a source which is operatively connected to a ground potential. In this case, the control circuit may further include a comparator which compares a reference voltage and the bias output. The comparator connects the gate of the P-channel transistor with the ground potential without connecting the gate of the N-channel transistor with the power supply potential when the bias output is lower than the reference voltage, and connects the gate of the N-channel transistor with the power supply potential and disconnects the gate of the P-channel transistor from the ground potential when the bias output is higher than the reference voltage.
Also, the biasing circuit may further include a timer connecting the gate of the P-channel transistor with the ground potential in response to a control signal, and after a predetermined time, disconnecting the gate of the P-channel transistor from the ground potential and connecting the gate of the N-channel transistor with the power supply potential.
Also, the P-channel transistor may be turned on and the N-channel transistor may be turned off for a first period before the bias output reaches a reference voltage, and the P-channel transistor may be turned off and the N-channel transistor may be turned on for a second period following the first period.
Alternatively, the P-channel transistor maybe major to the N-channel transistor in the drive voltage for a first period before the bias output reaches a reference voltage, and the P-channel transistor may be minor to the N-channel transistor in the drive voltage for a second period following the first period. Thus, change from the P-channel transistor to the N-channel transistor may be gradually carried out. In this case, the P-channel transistor and the N-channel transistor may be different from each other in size. Also, a current ratio of the P-channel transistor to the N-channel transistor is in a range of 1:3 to 1:5.
Also, the gate of the P-channel transistor may be connected to a control signal which is active low. The supplying circuit may further include a second P-channel transistor having a source which is connected to the power supply potential, a gate which is operatively connected to the control signal, and a drain which is operatively connected to the drain of the N-channel transistor.
Alternatively, when the gate of the P-channel transistor is connected to a control signal which is active low, the supplying circuit may further include an inverter inverting the control signal to connect to the gate of the N-channel transistor.
Also, the control circuit feeds back a first gain when a difference between the bias output and a predetermined voltage is larger than a first voltage and feeds back a second gain smaller than the first gain when the difference between the bias output and a predetermined voltage is smaller than the first voltage.
In order to achieve another aspect of the present invention, a semiconductor memory device includes a memory cell connected with a word line and a digit line via a control circuit, an N-channel bias transistor and a drive circuit. The N-channel bias transistor supplies the memory cell via the control circuit with a bias voltage on the digit line to in response to a drive voltage when the word line is activated. The drive circuit includes a P-channel transistor and an N-channel transistor connected to each other -in parallel, and supplies the drive voltage to the bias transistor by the P-channel transistor and the N-channel transistor.
The P-channel transistor may have a source which is operatively connected to a power supply potential, a gate which is operatively connected to a ground potential, and a drain which is operatively connected to the bias outputting circuit. Also, the N-channel transistor may have a drain which is operatively connected to the power supply potential, a gate which is operatively connected to the power supply potential, and a source which is operatively connected to the bias outputting circuit.
The drive circuit may further includes an N-channel control transistor having a drain which is connected to the drain of the P-channel transistor and the source of the N-channel transistor, a gate which is operatively connected to the bias voltage from the bias transistor, and a source which is operatively connected to a ground potential.
Also, the P-channel transistor may be turned on when the bias voltage is much lower than a predetermined voltage and the N-channel transistor may be turned on when the bias voltage is substantially the same as the predetermined voltage.
Also, when an operation period of the drive circuit includes a first period and a second period following the first period, the P-channel transistor is major to the N-channel transistor in the drive voltage for the first period and the P-channel transistor is minor to the N-channel transistor in the drive voltage for the second period, and change from the P-channel transistor to the N-channel transistor is gradually carried out. In this case, the P-channel transistor and the N-channel transistor are different from each other in size. Also, a current ratio of the P-channel transistor to the N-channel transistor may be in a range of 1:3 to 1:5.
Also, when the gate of the P-channel transistor is connected to a control signal which is active low, the supplying circuit may further include a second P-channel transistor having a source which is connected to the power supply potential, a gate which is operatively connected to the control signal, and a drain which is operatively connected to the drain of the N-channel transistor.
Alternatively, when the gate of the P-channel transistor is connected to a control signal which is active low, the supplying circuit further includes an inverter inverting the control signal to connect to the gate of the N-channel transistor.
Also, the drive circuit feeds back a first gain when a difference between the bias output and a predetermined voltage is larger than a first voltage and feeds back a second gain smaller than the first gain when the difference between the bias output and a predetermined voltage is smaller than the first voltage.